1. Field of Invention
The present invention relates to integrated circuits (ICs) generally and more particularly to low-power IC systems.
2. Description of Related Art
IC Designs with multiple power domains are becoming increasingly common since power consumption can be reduced by temporarily powering off regions of the chip (called domains) that do not need to be active. Such designs have one or more switchable power domains and these domains can be powered off to eliminate both static and dynamic power dissipation in them. In order to ensure that the domain powers back on into a known state, switchable domains may include state retention cells (e.g., circuit elements that include retention elements for saving state values during power variations). Typically, state retention cells contain special flops or latches to retain the state of the cell when its main power supply is shut off. See, for example, U.S. Pat. Nos. 6,775,180, 7,091,766, 7,123,068, 7,164,301, 7,183,825, and 7,138,842, each of which is incorporated by reference herein in its entirety.
State retention cells, which are also called State Retention Power Gating or SRPG cells in some contexts, must be tested during manufacturing test to ensure that they are functioning correctly. An SRPG cell must be capable of retaining data when power is turned off to its enclosing domain, and the retained data must be observable once power is turned back on. In this context, a domain is considered switched off when the ambient voltage is lower than the operating voltage of the domain so that the ambient voltage does not necessarily have to be at 0V for the domain to be switched off.
But the tests currently generated by Automatic Test Pattern Generation (ATPG) tools generally do not target the retention capabilities of the SRPG cells. In general, these tests target only structural defects (net stuck at logic-0 value, etc.) in the chip, and do not try to test the functional behavior of the logic including, for example, cycling of the power domains (e.g., turning them off and back on) containing the SRPG cells to see whether the cells are retaining state or not. See, for example, U.S. Pat. No. 7,065,724, which is incorporated by reference herein in its entirety.
Hence there is a need to test SRPG cells using a ‘functional’ approach that will involve testing the state retention capability of the SRPG in addition to testing just for structural defects. More generally there is a need for improved testing of ICs with retention elements for saving values during power variations related to the ICs.